Optical isolators, also known as opto-isolators, optical couplers and opto-couplers, are circuits or devices that are often included in analog-to-digital conversion circuits and similar circuits for sensitive instrumentation and control applications. For example, such a conversion circuit is commonly used to sense motor current or voltage in motor control applications. Isolating the conversion circuit from the processing circuit to which the conversion circuit provides its output signal is intended to avoid the processing circuit inducing noise or voltage spikes in the sensitive conversion circuit. In many cases, the conversion circuit and processing circuit are coupled to different ground potentials, necessitating some form of isolation.
As illustrated in FIG. 1, a prior art analog-to-digital conversion device 10 can be used to sense an analog input such as current or voltage from, for example, a motor (not shown) to be controlled, and provide a digital output representing the sensed value to the motor control circuitry (not shown). A clock signal is provided as another input to device 10, as most analog-to-digital converters, especially those of the popular sigma-delta type, require a clock signal to operate properly. Two integrated circuit chips 12 and 14 are packaged together in an integrated manner to form device 10. Chip 12 includes the interface circuitry that can be used to connect device 10 to external processing circuitry, such as a motor control circuit (not shown), and chip 14 includes the conversion circuitry that can be used to connect device 10 to the motor voltage or current sensing circuit (not shown) or other means for sensing an analog input signal. A first opto-isolator 16, comprising a first light-emitting diode (LED) 18 and a first photodetector 20, couples the clock signal from chip 12 to chip 14. A second opto-isolator 22, comprising a second LED 24 and a second photodetector 26, couples the converted signal from chip 14 to chip 12. Note that in some instances photodetector 20 is included on chip 14, and photodetector 26 is included on chip 12.
Chip 12 includes an LED driver circuit 28 that drives LED 18, an LED receiver circuit 30 that receives the output of photodetector 26, and an output driver circuit 32 that transforms the converted signal into a suitable digital output signal for driving the external processing circuitry. Chip 14 includes an LED receiver circuit 34 that receives the output of photodetector 20, the analog-to-digital converter (ADC) 36 that receives the analog input signal and performs the conversion, and an LED driver circuit 38 that drives LED 24 with the digital output of ADC 36.
ADC 36 is of the sigma-delta type because such a converter can be made to operate at high conversion speed, high precision and low power. Also, with its natural low-pass filter characteristic, this type of ADC is most suitable for noisy industrial environments. Input clock signal speeds on the order of 10 MHz are typical (as illustrated in FIG. 1). However, such a circuit is not without drawbacks. To operate at high conversion speed and precision, opto-isolators 16 and 22 need to be correspondingly high-speed devices, and high-speed opto-isolators are less economical than low-speed opto-isolators that provide equivalent performance. Also, the higher the clock speed, the greater the adverse impact of electrical and optical imperfections in the optical channel; a chip design that seeks to avoid clock jitter and high-frequency transients across a high-speed optical channel taxes various resources, driving up design and manufacturing cost. It would be desirable to maximize manufacturing economy without sacrificing conversion performance. Also, LED driver circuits 28 and 38 consume correspondingly high current at such high clock speeds. It would likewise be desirable to minimize current consumption without sacrificing conversion performance. Another problem with device 10 is that while a duty cycle of exactly 50 percent is optimal for performance of ADC 36, the high-speed optical channel can undesirably deform the 50% duty cycle of the input clock signal.
To address some of the challenges described above, such as ensuring a 50% duty cycle, the modified device 10′ illustrated in FIG. 2 has been developed. Device 10′ is identical to device 10 with the exception of the inclusion of a divide-by-two circuit 40. The input clock signal has a frequency twice that at which ADC 36′ operates. Thus, for example, if it is desired to operate ADC 36′ at a frequency of 10 MHz as in the example discussed above with regard to FIG. 1, a 20 MHz clock signal is input to device 10′. Divide-by-two circuit 40 divides the clock signal down to 10 MHz before providing it to ADC 36′ and, in doing so, restores a 50% duty cycle to the signal. A drawback of device 10′, however, is that the optical channel defined by opto-isolator 16′ operates at 20 MHz (or 40 megabaud (Mbaud), i.e., 40 million symbol transitions per second), which is even higher than the rate of 10 MHz (or 20 Mbaud) that was already high enough to tax manufacturing and chip resources and accordingly adversely impact manufacturing economy. Device 10′ consumed even more power, used more silicon area, and required an even faster opto-isolator 16′ than device 10.
It would be desirable to provide an economical, high-performance, low-power, optically isolated device of the type described above. The present invention addresses these problems and deficiencies in the manner described below.